The UCSC Kestrel parallel processor
نویسندگان
چکیده
منابع مشابه
The UCSC Kestrel General Purpose Parallel Processor
The UCSC Kestrel Project has built a single-board programmable parallel processor with 512 processing elements (PEs). The fully operational system features a dense 1.4 million transistor chip composed of 64 byte-wide PEs, each with its own memory. The system architecture was designed speci cally to support a large variety of computational biology algorithms, for which programmability was essent...
متن کاملSession S3A THE UCSC KESTREL HIGH PERFORMANCE SIMD PROCESSOR: PRESENT AND FUTURE
The UCSC Kestrel parallel processor is a single-board linear array processor with 512 8-bit processing elements. In the process of building the machine, we have touched nearly all aspects of computer engineering, from VLSI layout to board design and debugging, and from device drivers to new algorithm development. The programmable array is primarily designed for several core algorithms from comp...
متن کاملMolecular Fingerprinting on the SIMD Parallel Processor Kestrel
In combinatorial library design and use, the conformation space of molecules can be represented using three-dimensional (3-D) pharmacophores. For large libraries of flexible molecules, the calculation of these 3-D pharmacophoric fingerprints can require examination of trillions of pharmacophores, presenting a significant practical challenge. Here we describe the mapping of this problem to the U...
متن کاملSequence Analysis With the Kestrel SIMD Parallel Processor
Computer aided sequence analysis is a critical aspect of current biological research. Sequence information from the genome sequencing projects fills databases so quickly that humans cannot examine it all. Hence there is a heavy reliance on computer algorithms to point out the few important nuggets for human examination. Sequence search algorithms range from simple to complex, as does the repres...
متن کاملKestrel: Design of an 8-bit SIMD Parallel Processor
Kestrel is a high-performance programmable parallel co-processor. Its design is the result of examination and reexamination of algorithmic, architectural, packaging, and silicon design issues, and the interrelations between them. The nal system features a linear array of 8-bit processing elements, each with local memory, an arithmetic logic unit (ALU), a multiplier, and other functional units. ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IEEE Transactions on Parallel and Distributed Systems
سال: 2005
ISSN: 1045-9219
DOI: 10.1109/tpds.2005.12